The present invention relates to a semiconductor device and concerns, for example, a semiconductor device having a DLL (Delay Locked Loop) circuit.
A conventionally known technique reduces the size of a circuit that generates a signal for controlling the operation timing of a semiconductor device.
For example, a clock tree circuit described in Japanese Patent Laid-Open No. 2005-44854 includes a first partial clock tree that distributes a clock through a first clock driver, and a second partial clock tree that distributes a clock through a second clock driver. Furthermore, the clock tree circuit includes a phase comparator that compares the phases of a first clock from the first partial clock tree and a second clock from the second partial clock tree, and a low-pass filter that receives the output of the phase comparator and converts the output into a direct current. At least one of the first and second clock drivers has a variable delay time. The clock tree circuit is configured to control the delay time of at least one of the first and second clock drivers with a delay time variable according to the output of the low-pass filter.